If you are in the technology domain, regardless of your department, I’m sure you must have come across discussions that include the word RISC, particularly RISC-V and a lot of articles and videos are being published about “ARM vs RISC”. Let’s decode the buzz and analyze whether it’s all hype or if it’s really worth your time to learn or even dive deep into RISC-V.
Microprocessors
Well, the word Microprocessor (µP) doesn’t need a formal introduction today as it has become the oxygen for technical and economical advancements in the modern world. Literally everyone is carrying at least one with them today in the form of mobile, bluetooth headsets, a calculator or a laptop. Before you jump in and recall Micro-controllers (µC), I want to add that a µC also has a µP inside it.
In case you are yet to learn about it, or want to revise the meaning of a µP, here’s what Wikipedia has to say about it:
A microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system.
The first µP, the Intel 4004, was introduced in 1971. The 4004 was a 4-bit processor consisting of approximately 2300 transistors with a clock frequency of just over 100 kilohertz (kHz). Its primary application was for building calculators.
Now let me present the technical definition of a µP (borrowed from Modern Processor Design by John & Mikko):
Microprocessors are instruction set processors (ISPs).
An ISP (the µP) executes instructions from a predefined instruction set. A µP functionality is fully characterized by the instruction set that it is capable of executing. All the programs that run on a µP are encoded in that instruction set. This predefined instruction set is also called the instruction set architecture (ISA).
If you have to build a µP, the first thing you need to decide is which ISA it will support. Ideally a µP adheres to a single ISA. A µP is typically designed and hardwired to support a specific ISA, such as x86, ARM, RISC-V, or MIPS.
Instruction Set Architecture (ISA)
Instruction set architecture plays a crucial role and is defined as a contract between software and hardware, or between the program and the machine. By having the ISA as a contract, programs and machines can be developed independently. Developers can write software that target the ISA without requiring knowledge of the the actual machine implementation (e.g., combinational and sequential logic circuits).
The ISA defines the supported data types, the registers, how the hardware manages main memory, key features (such as virtual memory), the instructions a microprocessor can execute, and the input/output model of multiple ISA implementations. The ISA can be extended by adding instructions or other capabilities, or by adding support for larger addresses and data values.
Machines can be designed that implement the ISA without concern for what programs will run on them. Any program written for a particular ISA should be able to run on any machine implementing that same ISA. The instruction set architecture specifies the functionality that must be implemented by the instruction set processor. The ISA plays several crucial roles in instruction set processor design.
CISC
Complex Instruction Set Computing consists of complex instructions using which a complex task can be executed in fewer instructions. But this in-turns require complex circuits and consumes more power.
The first CISC processors emerged in the 1970s, with the goal of reducing the number of instructions that a processor needed to execute a given task. This was achieved by creating complex instruction sets that could perform multiple operations in a single clock cycle. However, as processor complexity increased, it became clear that this approach had its limitations.
The Intel x86 ISA, is a type of the CISC architectures. The Intel x64 is an extension of the x86 architecture, used in 64-bit computing applications.
RISC
Reduced Instruction Set Computing consists of simple instructions that can be executed in large numbers to complete a complex task.
In the 1980s, the RISC architecture was introduced as a response to the growing complexity of CISC processors. RISC processors were designed to execute a smaller number of simpler instructions, with the goal of improving performance and reducing power consumption. The RISC architecture was pioneered by researchers at Stanford and Berkeley, who developed the first RISC processors, including the MIPS and SPARC architectures.
The ARM & MIPS ISAs are the variants of the the RISC ISA.
Arm is also a company that licenses it’s instruction set architectures to processor manufactures and that’s how it makes money. Arm stands for Advanced RISC Machines.
Popular ISAs
Since the advent of computers, a wide variety of ISAs have been developed and used. They differ in how operations and operands are specified. Typically an ISA defines a set of instructions called assembly instructions. Each instruction specifies an operation and one or more operands. Each ISA uniquely defines an assembly language.
There are several different ISAs being developed and used, the most popular and the prominent ones are listed in the table below.
| Year | ISA | Origin | Popular Usage Today |
|---|---|---|---|
| 1978 | x86 | Introduced by Intel 8086; became dominant for PCs and servers | PCs, laptops, many servers (Intel, AMD) |
| 1983 | ARM | Originally from Acorn Computers (UK); later spun off into ARM Ltd | Mobile phones, tablets, embedded, Apple M-series |
| 1985 | MIPS | Developed by Stanford/MIPS Computer Systems; pioneered RISC design | Embedded systems, routers, academic use |
| 2010 | RISC-V | Born at UC Berkeley as an open-source RISC ISA | Academia, startups, growing in edge/AI chips |
RISC vs CISC
Here is a quick comparison between RISC and CISC instruction set architectures.
| RISC | CISC | |
|---|---|---|
| Instruction Set | Simple, load/store architecture | Complex, microcode-based |
| Number of Instructions | Small ( tens to hundreds) | Large (thousands) |
| Instruction Length | Fixed | Variable |
| Pipelining | Easy to implement | Difficult to implement |
| Instruction | Set | Simple complex |
| Number of Instructions | Small | Large |
| Pipelining | Easy | Difficult |
| Power Consumption | Low | High |
| Code Size | Large | Small |
RISC-V Origins
The evolution of RISC architecture is one of the most important and transformative stories in computer architecture history.
In the late 1970s, John Cocke at IBM led the development of the IBM 801 processor, advocating for a simplified instruction set to improve processor efficiency, which laid the groundwork for RISC. The IBM 801, released in 1980, featured pipeline architecture and a reduced instruction set. John Cocke is widely regarded as the “father of RISC” and received multiple prestigious awards, including the ACM Turing Award and the National Medal of Science.
IBM’s PowerPC, a descendant of the 801, was a RISC-based processor used in Apple Macintosh computers from 1994 to 2005.
In parallel, David Patterson and Carlo H. Sequin led the UC Berkeley RISC project in the early 1980s, producing RISC-I in 1982, a 32-bit processor with a minimal instruction set. The Berkeley RISC project inspired later processors like ARM and continued with RISC-II, RISC-III (SOAR), and RISC-IV (SPUR), heavily influencing the RISC ecosystem.
Despite RISC origins in academia, most popular RISC ISAs like ARM, PowerPC, and MIPS are proprietary, creating issues around licensing costs, customizability, and tooling. The lack of standardization across RISC processors creates fragmentation, making it hard for developers and engineers to build compatible products. To address these issues, Krste Asanović, Yunsup Lee, and Andrew Waterman at UC Berkeley launched the RISC-V project in 2010.
RISC-V, the fifth generation of Berkeley RISC (pronounced “risk five”) is an open, modular, and extensible ISA, now governed by the RISC-V International Association based in Switzerland. Using RISC-V attracts no license or royalty fees i.e., companies don’t have to pay anyone to develop RISC-V-based products.
RISC-V was practically a baby among ISAs. Work on RISC-V commenced in 2010 in Berkeley’s Parallel Computing Lab (or Par Lab for short), which received funding from Microsoft as well as Intel, the creator of the x86 ISA. By 2011, the first RISC-V prototype was ready to be manufactured. RISC-V transformed from a research project into an actual ISA that companies could use in 2014 when David Patterson and Krste Asanović published a paper arguing that open-source hardware was the future and that RISC-V was the ISA to do the job. A year later, the RISC-V Foundation was created.
Current State of RISC-V
1There are over 3,500 members of RISC-V International, up from 600 at the start of 2020, 1,500 in early 2021, and 2,200 in late 2021. As for actual market share, it’s hard to say, but in May 2023 RISC-V CTO Mark Himelstein claimed “10s of billions” of RISC-V cores had been sold by member companies, which is in line with predictions for 2022 and 2023.
The introduction of RISC-V led to the foundation of companies that deal exclusively in RISC-V chips. SiFive is one of the most visible as the first company to make a RISC-V chip, and has a very similar business model to Arm, licensing out its custom RISC-V designs in order to turn a profit. Today, SiFive advertises its technology’s uses in wearables, cars, and a plethora of other areas. Furthermore, companies that once used other ISAs have made the full transition to using RISC-V; Microsemi, a subsidiary of Microchip, replaced ARM cores in its FPGAs with RISC-V cores.
2Thanks to the US-China conflict, Alibaba, Baidu and other Chinese companies have invested in building RISC-V chips to reduce their dependence on Intel’s x86 ISA (US) and the ARM ISA (UK-based) for a while now. Countries worldwide are increasingly aware that access to semiconductor IP, raw materials, manufacturing facilities, and finished products might be restricted in future.
As a result, countries are investing billions of dollars in strengthening their own semiconductor technologies and manufacturing capabilities. In April 2022, the Government of India announced a Digital India RISC-V (DIR-V) program. In December 2022, the EU announced it would release €270 million in funds for companies building chips based on the open RISC-V ISA.
State of RISC-V in India
India has been moving swiftly in the electronics domain since the early 2020s with concrete academic and official contributions showcasing India’s RISC‑V R&D efforts. India is not just adopting RISC‑V, it is actively innovating, commercializing, and shaping its future on the global stage.
- Shakti‑T: A RISC‑V Processor with Light Weight Security Extensions.
- In February 2025, IIT Madras and ISRO successfully booted a 64‑bit indigenous RISC‑V controller (IRIS), featuring fault‑tolerant internal memory
- C‑DAC’s VEGA series includes 32/64‑bit superscalar RISC‑V processors with MMU, multicore, cache, and coherent interconnects.
- The ARIES ALPHA v1.0 dev‑board is built around the THEJAS32 SoC featuring VEGA ET1031 RISC‑V core.
- Digital India RISC‑V (DIR‑V) Program: Announced in 2022 by MeitY, aiming to stimulate indigenous RISC‑V processor development, including SHAKTI, VEGA, and Ajit (IIT Bombay) processors.
Conclusion
It’s clear that there are immense opportunities to innovate and shape the future of technology powered by RISC architectures. With RISC-V being an open-source ISA, you have the freedom to explore, enhance, or even add your own custom instructions.
You can now take things a step further by building your own processors and boards, without the burden of paying royalties to anyone. The possibilities are truly endless.
Here’ what XDA-developers has to say about the RISC-V:
It’s obvious that RISC-V has a ton of momentum behind it, even if it’s not quite living up to its lofty ambitions. With thousands of members including some of the world’s leading computing companies, universities, and even India’s Ministry of Electronics and Information Technology, it’s hard to see RISC-V not becoming a major player on the computing scene. Perhaps in a few years, people will be arguing about whether ARM or RISC-V is the best for smartphones.
There’s no better time than now to start exploring RISC-V. Here are some great resources to help you get started:
- RISC-V Official Website – For specs, news, and tools straight from the source.
- The RISC-V Reader by Patterson & Waterman – A beginner-friendly book written by the creators of RISC-V.
- Ripes Simulator – A visual CPU pipeline simulator perfect for hands-on learning.
- RISC-V Academy – Free courses on RISC-V from universities and companies.
- SiFive Learn – Interactive tutorials and development boards from one of the core contributors to RISC-V.
- RISC-V: An Open Standard Instruction Set Architecture - By Mark Himelstein, CTO of RISC-V International is a great read about the present and future goals of RISC-V
Now is the perfect time to dive in and start building. Whether you’re a student, engineer, or enthusiast, RISC-V is open to everyone.
Keep building. 🔧💡
Footnotes
The section Current State of RISC-V are taken from: